Technology Foundation

H-PHY™ Architecture Overview

Energy-Efficient · Short-Reach Optimized · Technology-Scalable

H-PHY is designed to minimize CV2 switching energy through ultra-low-swing signaling, enabling energy-efficient, high-bandwidth, and scalable connectivity for wide I/O and next-generation short-reach interconnects.

NRZ Signaling

Current-Domain NRZ Signaling
H-PHY TX(HR-SST Driver)
H-PHY TX HR-SST driver, current-mode NRZ signaling, ultra-low swing
Ultra Low Swing
Short-Reach Channel(Interposer / Chiplet)
Current-Domain NRZ Signaling
H-PHY RX(CC Receiver)
H-PHY RX CC receiver, current-mode NRZ signaling, ultra-low swing
Ultra Low Swing

DC-Balanced PAM Signaling

Symbol Encoder(DC-Balanced)
Symbol encoder DC-balanced data lanes
Current-Domain PAM Signaling
H-PHY TX(HR-SST Driver)
H-PHY TX HR-SST driver, current-mode PAM multilevel signaling, ultra-low swing
Ultra Low Swing
Short-Reach Channel(Interposer / Chiplet)
Current-Domain PAM Signaling
H-PHY RX(CC Receiver)
H-PHY RX CC receiver, current-mode PAM multilevel signaling, ultra-low swing
Ultra Low Swing
Symbol Decoder(DC-Balanced)
Symbol decoder DC-balanced data lanes
01

Symbol Encoder(DC-Balanced Encoding)

  • Lightweight Encoding
  • Lane Coordination
  • Skew Management
02

H-PHY TX(HR-SST Driver)

  • High-Resistance SST Driver
  • Ultra-Low Swing
  • Low Energy per Bit
03

Short-Reach Channel(Interposer / Chiplet)

  • Reduced RC Sensitivity
  • Low Loss, Low Crosstalk
  • Low Skew Variation
04

H-PHY RX(CC Receiver)

  • RX-Centric Receiver
  • Wide Bandwidth
  • Low Power
05

Symbol Decoder(DC-Balanced Decoding)

  • Error Detection
  • Lane Reconstruction
  • De-Skewing
Technology-Key Characteristics
Extreme Energy Efficiency

Up to 10x better pJ/bit than conventional PHY

Optimized for Short-Reach Interconnects

Designed for interposer, package, and chiplet interconnects within short-reach environments

Compact & Scalable

Compact per-channel architecture designed for scalable multi-lane integration

Robust Signal Integrity

Designed to mitigate SSN, PDN disturbance, crosstalk, jitter, and skew variation

Technology-Scalable

Designed to scale with advanced process nodes and increasing data rates

Transmission Line Insertion Loss (S₂₁) vs. Frequency

Bandwidth Extension with DC-Balanced PAM Signaling

Transmission Line Insertion Loss (S21) vs Frequency: NRZ effective to -3 dB, DC-Balanced PAM extended to -10 dB

NRZ Signaling: Reference operating range up to approximately −3 dB channel lossDC-Balanced PAM Signaling: Extended operating range toward approximately −10 dB channel loss in the evaluated configuration

Conceptual illustration. Actual channel-loss tolerance depends on signaling conditions, interconnect characteristics, and system implementation.

Presented at the 2026 Symposium
on VLSI Technology & Circuits

0.06pJ/bit
Ultra-Low Energy
22.9Gb/s/pin
High Data Rate
0.006mm2/TL
Compact Silicon Footprint
14nmCMOS
Advanced-Node Scalability

S. Han et al., Symp. on VLSI, 2026, pp. 1-3
DOI: 10.1109/VLSITechnologyandCir65830.2026.11577423
View on IEEE Xplore® →

Architecture

RX-Centric Current-Domain Transceiver

H-PHY employs an RX-centric current-domain architecture based on a Current Conveyor (CC) receiver.

Conventional Op-Amp

Voltage-Mode, High-Gain Architecture

Conventional Op-Amp architecture: Vin through High Gain and Miller Compensation (Cc) to Vout with global feedback
  • Requires very high open-loop gain
  • Miller compensation limits bandwidth
  • Large input RC delay
  • Multiple gain stages and more poles
  • Higher power consumption and slower response
H-PHY Current Conveyor

Current-Mode, Unity Tracking Architecture

H-PHY Current Conveyor architecture: Y (High-Z) through Voltage Buffer (Vx=Vy) and Current Mirror (Iz=±Ix) to Z (High-Z) with local feedback
  • No high open-loop gain requirement
  • No or minimal Miller compensation, supporting wideband operation
  • Ultra-low X-port resistance (Rx ≈ 0 Ω)
  • Simplified signal path with fewer poles
  • Lower power and faster transient response
Limited(GBW tradeoff) Bandwidth Up to 10× Wider
Slower Propagation Delay Significantly Faster
Higher CV2 Power Efficiency Ultra Low CV2,
Lower Energy/bit
Compensation and stability limits Scalability Optimized for Advanced PHYs
Advantages of Current Conveyor

Current Conveyor–Enabled Low-Swing, Ultra-Low-Energy Interconnect

01

No Very-High Open-Loop Gain Requirement

Reduces dependence on conventional gain-bandwidth tradeoffs

02

Minimal Compensation Requirement

No or minimal Miller compensation, supporting wider bandwidth

03

Current-Domain Signal Processing

Reduced sensitivity to interconnect RC effects

04

Ultra-Low X-Port Resistance

Rx ≈ 0 Ω for interconnects

05

Simplified Architecture

Fewer gain stages,
shorter delay

06

Local Feedback

Faster settling and better stability

07

Wideband High-Frequency Operation

Advanced-Node Scalable 10–100 GHz Wideband Operation

08

Reduced Pole Count

Simpler dynamics
and wider bandwidth

09

Fast Transient Response

Fast settling with reduced propagation delay

10

Optimized for Advanced PHYs

Applicable to HBM, chiplet, and Wide I/O interconnects